1. Field of Invention
The present invention relates to a semiconductor packaging method and, in particular, to a one-step semiconductor stack packaging method.
2. Related Art
As electronic products become lighter, thinner, shorter and smaller, semiconductor packaging methods are also developed toward high densities and multi-functions. Small sizes but more capabilities have become the basic requirements for electronic products and semiconductor packaging. How to increase the semiconductor packaging density so as to promote the capabilities of the packaging elements while at the same time to decrease the complexity and cost in manufacturing has long been the target that semiconductor packaging industries are after. Stack type semiconductor packaging places elements or chips in a pile and thus is able to provide a higher packaging density and more functions than conventional planar packaging methods. A conventional technique for semiconductor stack packaging, such as the lead frame type stack packaging disclosed in the U.S. Pat. No. 5,811,877, packages chips in an ultra-thin lead frame and molds it into a thinner packaging device. Such devices are then stacked together and the pins of the lead frames are electrically connected. The manufacturing process is simple and has been widely used in semiconductor stack packaging. However, there are still some drawbacks that limit its development. For example, the packaging using lead frames is limited in its finite thickness and cannot be made to extremely thin. Furthermore, the electrical connections among stack devices can only achieved through the pins of the lead frames. The U.S. Pat. No. 5,222,014 also discloses a semiconductor stack packaging method, which needs to grow solder bumps on the top and bottom surfaces of a lower chip carrier substrate and solder bumps on the bottom surface of an upper chip carrier substrate. After the two chip carrier substrates are then aligned and stacked together, a reflow step is performed to achieve the electrical and mechanical connections between the two substrates. Since this method has to grow solder bumps on the top and bottom surfaces of all the chip carrier substrates except for the top one, the manufacturing process is much more complicated.
Therefore, it is highly desirable to provide a new semiconductor stack packaging method to improve existing technologies.
Accordingly, it is an objective of the invention to provide a one-step semiconductor stack packaging method to increase semiconductor packaging densities and to lower the complexity and cost of manufacturing.
Pursuant to the above objective, the present invention uses a one-step packaging method to stack and package a plurality of semiconductor packaging elements. According to a preferred embodiment of the invention, the top surface of each chip carrier substrate (opposite side to the chip) in the semiconductor packaging element is implanted with solder balls or applied with solder paste. After the plurality of semiconductor packaging elements are aligned and stacked, a reflow is applied to achieve electrical and physical connections among all substrates. This type of one-step stack packaging can simultaneously satisfy the requirements of high packaging densities, simple manufacturing processes and low costs.
The above semiconductor packaging elements can be the same or different semiconductor elements or semiconductor elements packaged in the same or different ways. A proper wiring and layout of I/O pads of the substrate can be prepared in advance according to the practical situation, rendering versatile applications.
In accordance with the invention, the disclosed one-step stack packaging method includes the following steps: prepare several semiconductor packaging elements, each of which is composed of a substrate and at least one chip with the substrate having an upper surface and a lower surface, the chip being installed on the lower surface of the substrate, and the substrate has been finished in a layout of wiring and proper I/O pads in advance; coat a soldering flux on the I/O pads on the upper surface of the substrate; dispose solder balls on the upper surface of the substrate; align and stack the semiconductor packaging elements; and reflow the stacked semiconductor packaging elements to complete the electrical connections among the substrates.
The steps of coating a soldering flux and disposing solder balls on the I/O pads can be replaced with coating tin gel by printing.
The I/O pads may or may not have via holes. The via holes can be filled with some filling material. The substrate can be a single-layer board, a multi-layer board, a flexible substrate or a rigid substrate.
In the above method, the semiconductor packaging element can be refined into ultra-thin elements. If the I/O pads of the substrate has via holes, one only needs to implant solder balls or apply solder paste on the I/O pad on the substrate top surface of the top semiconductor packaging element and the I/O pad on the substrate bottom surface of the bottom semiconductor packaging element. The reflow step can make the soldering material permeate through all layers of substrates, achieving electrical connections among the substrates.
Other features and advantages of the present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings.